学步园

• Modules are the building blocks of Verilog designs //module 是Verilog中的构成block
• You create the design hierarchy by instantiating modules in other modules. //你可以通过其他模块中实例化模块来完成层次化的设计
• You instance a module when you use that module in another, higher-level module. 你在一个层的模块中实例化一个模块

• Ports allow communication between a module and its environment. //端口允许模块和其所在的环境通信
• All but the top-level modules in a hierarchy have ports. //除了最上层的模块外，所有的模块都有端口
• Ports can be associated by order or by name.      //端口可以通过次序关联也可以通过名字关联

You declare ports to be input, output or inout. The port declaration syntax is : //你可以将端口方向声明为 input、output、inout方式，端口的声明语法如下：

input [range_val:range_var] list_of_identifiers;

output [range_val:range_var] list_of_identifiers;

inout [range_val:range_var] list_of_identifiers;

NOTE : As a good coding practice, there should be only one port identifier per line, as shown below

注意： 作为一个编码的好习惯，最好一行声明一个标识符，如下所示：

 1 input              clk       ; // clock input
 2 input  [15:0]      data_in   ; // 16 bit data input bus
 3 output [7:0]       count     ; // 8 bit counter output
 4 inout              data_bi   ; // Bi-Directional data bus

You could download file port_declare.v here

  1 module addbit (
  2 a      , // first input
  3 b      , // Second input
  4 ci     , // Carry input
  5 sum    , // sum output
  6 co       // carry output
  7 );
  8 //Input declaration
  9 input a;
 10 input b;
 11 input ci;
 12 //Ouput declaration
 13 output sum;
 14 output co;
 15 //Port Data types
 16 wire  a;
 17 wire  b;
 18 wire  ci;
 19 wire  sum;
 20 wire  co;
 21 //Code starts here
 22 assign {co,sum} = a + b + ci;
 23 
 24 endmodule // End of Module addbit

You could download file addbit.v here

Here order should match correctly. Normally it's not a good idea to connect ports implicitly. It could cause problem in debug (for example: locating the port which is causing a compile error), when any port is added or
deleted.

这样顺序必须匹配正确。通常，隐式关联端口不是一个注意。这样有可能在debug中引起问题（如定位端口错误由编译错误引起）， 当添加或删除了一个端口后。

  1 //-----------------------------------------------------
  2 // This is simple adder Program
  3 // Design Name : adder_implicit
  4 // File Name   : adder_implicit.v
  5 // Function    : This program shows how implicit
  6 //               port connection are done
  7 // Coder       : Deepak Kumar Tala
  8 //-----------------------------------------------------
  9 module adder_implicit (
 10 result        , // Output of the adder
 11 carry         , // Carry output of adder
 12 r1            , // first input
 13 r2            , // second input
 14 ci              // carry input
 15 );
 16 
 17 // Input Port Declarations       
 18 input    [3:0]   r1         ;
 19 input    [3:0]   r2         ;
 20 input            ci         ;
 21 
 22 // Output Port Declarations
 23 output   [3:0]  result      ;
 24 output          carry       ;
 25 
 26 // Port Wires
 27 wire     [3:0]    r1        ;
 28 wire     [3:0]    r2        ;
 29 wire              ci        ;
 30 wire     [3:0]    result    ;
 31 wire              carry     ;
 32 
 33 // Internal variables
 34 wire              c1        ;
 35 wire              c2        ;
 36 wire              c3        ;
 37 
 38 // Code Starts Here
 39 addbit u0 (
 40 r1[0]           ,
 41 r2[0]           ,
 42 ci              ,
 43 result[0]       ,
 44 c1
 45 );
 46 
 47 addbit u1 (
 48 r1[1]          ,
 49 r2[1]          ,
 50 c1             ,
 51 result[1]      ,
 52 c2
 53 );
 54 
 55 addbit u2 (
 56 r1[2]          ,
 57 r2[2]          ,
 58 c2             ,
 59 result[2]      ,
 60 c3
 61 );
 62 
 63 addbit u3 (
 64 r1[3]          ,
 65 r2[3]          ,
 66 c3             ,
 67 result[3]      ,
 68 carry
 69 ); 
 70 
 71 endmodule // End Of Module adder  

You could download file adder_implicit.v here

Here the name should match with the leaf module, the order is not important.

这里通过名字关联子模块的端口，端口的顺序不在重要。

  1 //-----------------------------------------------------
  2 // This is simple adder Program
  3 // Design Name : adder_explicit
  4 // File Name   : adder_explicit.v
  5 // Function    : Here the name should match 
  6 // with the leaf module, the order is not important.
  7 // Coder       : Deepak Kumar Tala
  8 //-----------------------------------------------------
  9 module adder_explicit (
 10 result        , // Output of the adder
 11 carry         , // Carry output of adder
 12 r1            , // first input
 13 r2            , // second input
 14 ci              // carry input
 15 );
 16 
 17 // Input Port Declarations       
 18 input    [3:0]   r1         ;
 19 input    [3:0]   r2         ;
 20 input            ci         ;
 21 
 22 // Output Port Declarations
 23 output   [3:0]  result      ;
 24 output          carry       ;
 25 
 26 // Port Wires
 27 wire     [3:0]    r1        ;
 28 wire     [3:0]    r2        ;
 29 wire              ci        ;
 30 wire     [3:0]    result    ;
 31 wire              carry     ;
 32 
 33 // Internal variables
 34 wire              c1        ;
 35 wire              c2        ;
 36 wire              c3        ;
 37 
 38 // Code Starts Here
 39 addbit u0 (
 40 .a           (r1[0])        ,
 41 .b           (r2[0])        ,
 42 .ci          (ci)           ,
 43 .sum         (result[0])    ,
 44 .co          (c1)
 45 );
 46 
 47 addbit u1 (
 48 .a           (r1[1])        ,
 49 .b           (r2[1])        ,
 50 .ci          (c1)           ,
 51 .sum         (result[1])    ,
 52 .co          (c2)
 53 );
 54 
 55 addbit u2 (
 56 .a           (r1[2])        ,
 57 .b           (r2[2])        ,
 58 .ci          (c2)           ,
 59 .sum         (result[2])    ,
 60 .co          (c3)
 61 );
 62 
 63 addbit u3 (
 64 .a           (r1[3])        ,
 65 .b           (r2[3])        ,
 66 .ci          (c3)           ,
 67 .sum         (result[3])    ,
 68 .co          (carry)
 69 );
 70 
 71 endmodule // End Of Module adder

You could download file adder_explicit.v here

  1 //-----------------------------------------------------
  2 // This is simple parity Program
  3 // Design Name : parity
  4 // File Name   : parity.v
  5 // Function    : This program shows how a verilog
  6 //               primitive/module port connection are done
  7 // Coder       : Deepak
  8 //-----------------------------------------------------
  9 module parity (
 10 a      , // First input
 11 b      , // Second input 
 12 c      , // Third Input
 13 d      , // Fourth Input
 14 y        // Parity  output
 15 );
 16 
 17 // Input Declaration
 18 input       a       ;
 19 input       b       ;
 20 input       c       ;
 21 input       d       ;
 22 // Ouput Declaration
 23 output      y      ;
 24 // port data types
 25 wire        a        ;
 26 wire        b        ;
 27 wire        c        ;
 28 wire        d        ;
 29 wire        y        ;
 30 // Internal variables
 31 wire        out_0 ;
 32 wire        out_1 ;
 33 
 34 // Code starts Here
 35 xor u0 (out_0,a,b);
 36 
 37 xor u1 (out_1,c,d);
 38 
 39 xor u2 (y,out_0,out_1);
 40 
 41 endmodule // End Of Module parity 

You could download file parity.v here

Question : What is the difference between u0 in module adder and u0 in module parity?

前者通过名字关联，后者通过次序进行隐式关联。

• Inputs : internally must always be of type net, externally the inputs can be connected to a variable of type reg or net.
• input：输入内部一定要被指派为net类型网线型，外部驱动输入可以reg变量也可以是net类型变量
• Outputs : internally can be of type net or reg, externally the outputs must be connected to a variable of type net.
• 输出： 内部的可以是reg类型也可以是net类型，但输出的外部必须是net类型的变量
• Inouts : internally or externally must always be type net, can only be connected to a variable net type.
• inout： 内部和外部都必须是net类型只能连接到一个net型变量

• Width matching : It is legal to connect internal and external ports of different sizes. But beware, synthesis tools could report problems.
• 位长匹配： 端口内外不同的size合法；但是注意到综合时，会报错。
• Unconnected ports : unconnected ports are allowed by using a ",".
• 未连接的端口：为链接的端口可以同过，占位。
• The net data types are used to connect structure.
• net数据类型用来链接连个结构
• A net data type is required if a signal can be driven a structural connection.
• 如果一个信号能够驱动一个structural链接，一个net数据类型需要。

  1 module implicit();
  2 reg clk,d,rst,pre;
  3 wire q;
  4 
  5 // Here second port is not connected
  6 dff u0 ( q,,clk,d,rst,pre); 
  7 
  8 endmodule
  9 
 10 // D fli-flop
 11 module dff (q, q_bar, clk, d, rst, pre);
 12 input clk, d, rst, pre;
 13 output q, q_bar;
 14 reg q;
 15 
 16 assign q_bar = ~q;
 17 
 18 always @ (posedge clk)
 19 if (rst == 1'b1) begin
 20   q <= 0;
 21 end else if (pre == 1'b1) begin
 22   q <= 1;
 23 end else begin
 24   q <= d;
 25 end
 26 
 27 endmodule

You could download file implicit.v here

  1 module explicit();
  2 reg clk,d,rst,pre;
  3 wire q;
  4 
  5 // Here q_bar is not connected
  6 // We can connect ports in any order
  7 dff u0 (  
  8 .q  	(q),
  9 .d 	(d),
 10 .clk 	(clk),
 11 .q_bar 	(),
 12 .rst 	(rst),
 13 .pre 	(pre)
 14 );
 15 
 16 endmodule
 17 
 18 // D fli-flop
 19 module dff (q, q_bar, clk, d, rst, pre);
 20 input clk, d, rst, pre;
 21 output q, q_bar;
 22 reg q;
 23 
 24 assign q_bar = ~q;
 25 
 26 always @ (posedge clk)
 27 if (rst == 1'b1) begin
 28   q <= 0;
 29 end else if (pre == 1'b1) begin
 30   q <= 1;
 31 end else begin
 32   q <= d;
 33 end
 34 
 35 endmodule

You could download file explicit.v here