the above original link:http://www.asic-world.com/verilog/sys_task_func.html
Introduction //简介 | ||
There are tasks and functions that are used to generate input and output during simulation. Their names begin with a dollar sign ($). The synthesis tools parse and ignore system functions, and hence can be included even 在仿真(simulation)时,有一些任务task和函数function用来成生输入和输出。 它们的名字以$开始。综合工具解析或者忽略系统函数,因此可以包含在可以综合的模块中。 |
||
$display, $strobe, $monitor | ||
These commands have the same syntax, and display text on the screen during simulation. 这些命令有着相同的语法格式,并且能够在仿真期间在屏幕上显示文本。 They are much less convenient than waveform display tools like GTKWave. or Undertow or Debussy. 它们没有波形图显示工具(如GTKWave ,undertow , debussy)方便。 $display and $strobe display once every time they are executed, whereas $monitor displays every time one of its parameters changes. $display,$strobe 在每次执行时,显示一次。 然而,$monitor在每次其参数发生变化时都显示。 The difference between $display and $strobe is that $strobe displays the parameters at the very end of the current simulation time unit rather than exactly when it is executed. $dispaly和$strobe不同点在于,$strobe显示的参数是在当前仿真单元的结束而不是开始。 The format string is like that in C/C++, and may contain format characters. 格式化字符串和C、C++中的类似,可能包含格式化字符。 Format characters include %d (decimal), %h (hexadecimal), %b (binary), %c (character), %s (string) and %t (time), %m (hierarchy level). 格式化字符包括: %d (decimal), %h (hexadecimal), %b (binary), %c (character), %s (string) and %t (time), %m (hierarchy level). %5d, %5b etc. would give exactly 5 spaces for the number instead of the space needed. 显示的宽度设置。 Append b, h, o to the task name to change default format to binary, octal or hexadecimal. 在task name后加b,o,h可以讲默认的格式化方式变为binary,octal,或者hexadecimal。 |
||
Syntax 语法格式 | ||
|
||
$time, $stime, $realtime | ||
These return the current simulation time as a 64-bit integer, a 32-bit integer, and a real number, respectively. 这些任务返回当前的仿真时间的值,$time:64-bit integer,$stime : 32-bit integer, $realtime: a real number. |
||
$reset, $stop, $finish | ||
$reset resets the simulation back to time 0; $stop halts the simulator and puts it in interactive mode where the user can enter commands; $finish exits the simulator back to the operating system. $reset : 使simulation time(仿真时间)复位到0. $stop:挂起仿真器,使其进入交互模式,用户可以输入命令。 $finish: 退出仿真器,返回到os。 |
||
$scope, $showscope | ||
$scope(hierarchy_name) sets the current hierarchical scope to hierarchy_name. $scope(hierarchy_name):设置当期的层次作用域为hierarchy_name. $showscopes(n) lists all modules, tasks and block names in (and below, if n is set to 1) the current scope. $showscope(n) :显示当前作用域中所有的模块名字,task名字,block名字。 |
||
$random | ||
$random generates a random integer every time it is called. 每次调用$random时产生一个随机数。 If the sequence is to be repeatable, the first time one invokes random giving it a numerical argument (a seed). 如果这个序列是可重现的,在第一调用时给它传一个数值型参数(种子)。 Otherwise the seed is derived from the computer clock. 否则,种子源于计算机的时钟。 |
||
$dumpfile, $dumpvar, $dumpon, $dumpoff, $dumpall | ||
These can dump variable changes to a simulation viewer like Debussy. 这些系统任务可以将变量变化转储起来给仿真器查看器使用如Debussy。 The dump files are capable of dumping all the variables in a simulation. dump file能够转仿真时的所有变量。 This is convenient for debugging, but can be very slow. 这对于调试来说,非常方便,但是也是非常慢的。 |
||
Syntax | ||
|
||
$fopen, $fdisplay, $fstrobe $fmonitor and $fwrite | ||
These commands write more selectively to files. //这些命令可以更有选择性地写入到文件。 |
||
|
||
Syntax | ||
|
||
the above original link:http://www.asic-world.com/verilog/sys_task_func1.html