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PowerPC application-level instruction set

Table 1 lists different instruction categories and the types of instructions in each.

Table 1. Instruction categories

Deciphering an instruction

All instruction encodings are 32 bits in length. Bit numbering for PowerPC is the opposite of most other definitions: bit 0 is the most significant bit, and bit 31 is the least significant bit. Instructions are first decoded by the upper 6 bits in a field,
called theprimary opcode. The remaining 26 bits contain fields for operand specifiers, immediate operands, and extended opcodes, and these may be reserved bits or fields. PowerPC defines the basic instruction formats listed in Table 2.

Table 2. PowerPC instruction formats

• D-form
  This instruction format provides up to two registers as source operands, one immediate source, and up to two registers as target operands. Some variations of this instruction format use portions of the target and source register operand specifiers as immediate
  fields or as extended opcodes.
• X-form
  This instruction format provides up to two registers as source operands and up to two target operands. Some variations of this instruction format use portions of the target and source operand specifiers as immediate fields or as extended opcodes.
• A-form
  This instruction format provides up to three registers as source operands, and one target operand. Some variations of this instruction format use portions of the target and source operand specifiers as immediate fields or as extended opcodes.
• BD-form
  This instruction format is used by the conditional branch instruction. The BO instruction field specifies the type of condition; the BI instruction field specifies which CR bit is to be used as the condition; and the BD field is used as the branch displacement.
  The AA bit specifies whether the branch is an absolute or relative branch. That is, the branch target address is the value of the immediate field or is the sum of the value of the immediate field and the address of the branch. The LK bit specifies whether
  the address of the next sequential instruction is saved in the Link Register as a return address for a subroutine call.
• I-form
  This instruction format is used by the unconditional branch instruction. Being unconditional, the BO and BI fields of the BD format are exchanged for additional branch displacement to form the LI instruction field. This instruction format also supports the
  AA and LK bits in the same fashion as the BD format.

As mentioned, there are variations to these instruction formats. However, these formats best represent the makeup of most of the PowerPC instruction set encodings.

Branch instructions

PowerPC provides a set of instructions for control flow that include:

• Both conditional and unconditional branch instructions
• A "decrement count and branch if zero/not zero" capability
• Absolute and relative branching
• Branch instructions using the contents of the Link Register or Count Register to specify the branch target address

The ability to save the address of the next sequential instruction is provided on all branch instructions, including the Branch to Link Register instruction. Conditional branches allow specifying any one of the 32 Condition Register bits to be used as the condition,
and to specify whether that CR bit must be equal to 0 or 1 for the branch condition to succeed.

Condition register instructions

PowerPC provides a set of instructions for performing boolean operations on specific bits of the CR as well as copying CR fields. This allows the combining of multiple branching conditions, which can reduce the number of costly conditional branches. Table 3
lists PowerPC CR logical instructions.

Table 3. PowerPC CR logical instructions

Integer arithmetic instructions

Many instructions exist for performing arithmetic operations, including add, subtract, negate, compare, multiply, and divide. Many forms exist for immediate values, overflow detection, and carry in and out. Multiply and divide instruction performance varies
among implementations, as these are typically multi-cycle instructions. Table 4 lists PowerPC integer arithmetic instructions.

Table 4. PowerPC integer arithmetic instructions

Logical, rotate, and shift instructions

PowerPC provides a complete set of logical operations, and also provides support for sign-extension and counting the number of leading zeros in a GPR. Table 5 lists PowerPC logical instructions.

Table 5. PowerPC logical instructions

PowerPC provides a robust and powerful set of rotate and shift operations, as listed in Table 6.

Table 6. PowerPC rotate and shift instructions

Mnemonic

Instruction name

rldc[.]

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