This Verilog tutorial was started a long time ago. Every time I update my web page, I make sure
I add something new in the Verilog tutorial section. If you have been a frequent visitor, you should have noticed how these tutorial pages have improved. I hope some day this Verilog tutorial becomes a reference for all the engineers out there. Of course,
new learners will always find this tutorial useful. All the examples have been simulated using Icarus Verilog simulator. Currently this website is getting more than 1
million hits every month.
译文：
这个Verilog教程起源于很久以前。 每次更新我的web页，我都确保在Verilog教程部分添加一些新的内容。
如果你经常访问的话，你一定注意到了这个教程是怎样被改进的。
我希望将来这个Verilog教程能成为所有Verilog工程师的参考手册。
当然，Verilog的新手也总会发现该教程，非常有帮助。
涉及到的所有的例子，都是经过Icarus Verilog simulator （verilog仿真器）仿真测试过（后面再学习Icarus 工具的使用）。
目前，这个网站每个月有超过1million点击率。
A special
thanks to Paolo Franchetti for fixing grammar and spelling mistakes
in Verilog tutorial.
特别鸣谢Paolo
Franchetti为修改该教程中语法和拼写错误做出的贡献。
important
:This tutorial is best seen using firefox web browser and may not look well on Internet Explorer.
提示：该教程最好使用firefox
web browser 阅读；如果使用Internet Explorer（IE）可能带来不便。
教程目录：
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Introduction // 简介 | |
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Verilog In One Day //学习Verilog的第一天 | |
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History Of Verilog //Verilog的前生（历史） | |
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Design And Tool Flow //设计和工具流图 | |
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My first program in Verilog //我的第一个verilog程序 | |
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Verilog HDL Syntax And Semantics //verilog HDL（Hardware Description Language)的语法和语义 | |
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Gate Level Modeling //门级建模 | |
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User Defined Primitives //用户定义原语 | |
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Verilog Operators //verilog操作符 | |
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Verilog Behavioral Modeling //verilog的行为级建模 | |
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Procedural Timing Control //过程时间控制 | |
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Task And Functions //Task（任务）和 Function（函数） | |
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System Task and Function // 系统任务和系统函数 | |
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Art of Writing TestBenches //测试基准程序的编写（艺术）技巧 | |
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Modeling Memories And FSM //对 Memory 和FSM（有限状态机）的建模 | |
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Parameterized Modules //参数化的模块 | |
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Verilog Synthesis Tutorial //Verilog综合教程 | |
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Verilog PLI Tutorial //Verilog PLI教程 | |
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What's new in Verilog 2001 //Verilog2001中新增内容 | |
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Assertions In Verilog //Verilog中的断言 | |
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Compiler Directives // 编译器指令 | |
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Verilog Quick Reference // Verilog的快速参考手册 | |
the original link:http://www.asic-world.com/verilog/veritut.html