提示：
分析注释的部分，一般都会字体加粗或设置为红色字体。
本文包含如下代码：
mediatek/platform/mt6572/lk/platform.c
mediatek/platform/mt6572/lk/include/platform/mt_uart.h
mediatek/platform/mt6572/lk/uart.c
相关的寄存器资料请参考：
http://blog.csdn.net/duanlove/article/details/16862901
串口的使用过程：
1. 串口初始化，配置好波特率、工作模式及相关初始化寄存器。
2. 把需要发送的字符写入到串口发送寄存器。或者把串口接收寄存器里的东西读出来。
LK中的printf 就使用了 UART来发送我们程序中打印的log到串口。这样我们可以通过串口终端来查看 lk打印的log。
关于printf的细节请参考：
MT6572的LK printf 与UART串口打印 http://blog.csdn.net/duanlove/article/details/16898097
platform_early_init 函数是 MT6572平台 必须经过的一个初始化函数。
系统开机从preload预加载开始执行，然后把参数传入LK，并进入LK（类似于uboot），进行相应的初始化。串口的初始化便是在platform_early_init 函数里执行的。
在lk的 mediatek/platform/mt6572/lk/platform.c 里的 platform_early_init 函数中进行了串口的初始化。
void platform_early_init(void)
{
#ifdef LK_PROFILING
unsigned int time_led_init;
unsigned int time_pmic6329_init;
unsigned int time_i2c_init;
unsigned int time_disp_init;
unsigned int time_platform_early_init;
unsigned int time_set_clock;
unsigned int time_disp_preinit;
unsigned int time_misc_init;
unsigned int time_clock_init;
unsigned int time_wdt_init;
time_platform_early_init = get_timer(0);
time_set_clock = get_timer(0);
#endif
//mt_gpio_set_default();
//Specific for MT6572. ARMPLL can't set to max speed when L2 is configured as SRAM.
//preloader won't reach max speed. It will done by LK.
if (g_boot_arg->boot_mode != DOWNLOAD_BOOT)
{
mtk_set_arm_clock();
}
/* initialize the uart */
uart_init_early();
printf("arm clock set finished\n");
//printf实际上调用了串口发送的函数。具体请参考MT6572的LK printf 与UART串口打印
printf("uart_init_early init finished\n");
………………
}
uart_init_early() 函数的实现具体请看mediatek/platform/mt6572/lk/uart.c
/*
filename: mediatek/platform/mt6572/lk/uart.c
* Copyright (c) 2008 Travis Geiselbrecht
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
* (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <debug.h>
#include <reg.h>
#include <dev/uart.h>
#include <platform/mt_typedefs.h>
#include <platform/mt_reg_base.h>
#include <platform/mt_uart.h>
#include <platform/boot_mode.h>
#include <platform/mt_gpio.h>
#include <platform/sync_write.h>
#define CONFIG_BAUDRATE 921600
#define UART_SET_BITS(BS,REG) mt65xx_reg_sync_writel(DRV_Reg32(REG) | (u32)(BS), REG)
#define UART_CLR_BITS(BS,REG) mt65xx_reg_sync_writel(DRV_Reg32(REG) & ~((u32)(BS)), REG)
#define UART_BASE(uart) (uart)
#define UART_RBR(uart) (UART_BASE(uart)+0x0) /* Read only */
#define UART_THR(uart) (UART_BASE(uart)+0x0) /* Write only */
#define UART_IER(uart) (UART_BASE(uart)+0x4)
#define UART_IIR(uart) (UART_BASE(uart)+0x8) /* Read only */
#define UART_FCR(uart) (UART_BASE(uart)+0x8) /* Write only */
#define UART_LCR(uart) (UART_BASE(uart)+0xc)
#define UART_MCR(uart) (UART_BASE(uart)+0x10)
#define UART_LSR(uart) (UART_BASE(uart)+0x14)
#define UART_MSR(uart) (UART_BASE(uart)+0x18)
#define UART_SCR(uart) (UART_BASE(uart)+0x1c)
#define UART_DLL(uart) (UART_BASE(uart)+0x0) /* Only when LCR.DLAB = 1 */
#define UART_DLH(uart) (UART_BASE(uart)+0x4) /* Only when LCR.DLAB = 1 */
#define UART_EFR(uart) (UART_BASE(uart)+0x8) /* Only when LCR = 0xbf */
#define UART_XON1(uart) (UART_BASE(uart)+0x10) /* Only when LCR = 0xbf */
#define UART_XON2(uart) (UART_BASE(uart)+0x14) /* Only when LCR = 0xbf */
#define UART_XOFF1(uart) (UART_BASE(uart)+0x18) /* Only when LCR = 0xbf */
#define UART_XOFF2(uart) (UART_BASE(uart)+0x1c) /* Only when LCR = 0xbf */
#define UART_AUTOBAUD_EN(uart) (UART_BASE(uart)+0x20)
#define UART_HIGHSPEED(uart) (UART_BASE(uart)+0x24)
#define UART_SAMPLE_COUNT(uart) (UART_BASE(uart)+0x28)
#define UART_SAMPLE_POINT(uart) (UART_BASE(uart)+0x2c)
#define UART_AUTOBAUD_REG(uart) (UART_BASE(uart)+0x30)
#define UART_RATE_FIX_AD(uart) (UART_BASE(uart)+0x34)
#define UART_AUTOBAUD_SAMPLE(uart) (UART_BASE(uart)+0x38)
#define UART_GUARD(uart) (UART_BASE(uart)+0x3c)
#define UART_ESCAPE_DAT(uart) (UART_BASE(uart)+0x40)
#define UART_ESCAPE_EN(uart) (UART_BASE(uart)+0x44)
#define UART_SLEEP_EN(uart) (UART_BASE(uart)+0x48)
#define UART_VFIFO_EN(uart) (UART_BASE(uart)+0x4c)
#define UART_RXTRI_AD(uart) (UART_BASE(uart)+0x50)
//FIXME Disable for MT6572 LK Porting
#ifndef MACH_FPGA
#define __ENABLE_UART_LOG_SWITCH_FEATURE__
#endif
// output uart port
volatile unsigned int g_uart;
// output uart baudrate
unsigned int g_brg;
//extern unsigned int mtk_get_bus_freq(void);
#ifdef MACH_FPGA
#define UART_SRC_CLK 12000000
#else
#define UART_SRC_CLK 26000000
#endif
int mtk_uart_power_on(MTK_UART uart)
{
//FIXME Disable for MT6572 LK Porting
//return 0;
/* UART Powr PDN and Reset*/
//#define AP_PERI_GLOBALCON_RST0 (PERI_CON_BASE+0x0)
#define AP_PERI_GLOBALCON_PDN0 (0x10000084)
if (uart == UART1)
UART_SET_BITS(1 << 10, AP_PERI_GLOBALCON_PDN0); /* Power on UART1 */
else if (uart == UART2)
UART_SET_BITS(1 << 11, AP_PERI_GLOBALCON_PDN0); /* Power on UART2 */
return 0;
}
void uart_setbrg()
{
unsigned int byte,speed;
unsigned int highspeed;
unsigned int quot, divisor, remainder;
unsigned int uartclk;
unsigned short data, high_speed_div, sample_count, sample_point;
unsigned int tmp_div;
speed = g_brg; //921600
////FIXME Disable for MT6572 LK Porting
uartclk = UART_SRC_CLK;
//uartclk = (unsigned int)(mtk_get_bus_freq()*1000/4);
if (speed <= 115200 ) {
highspeed = 0;
quot = 16;
} else {
highspeed = 3;
quot = 1;
}
// 根据串口速率的等级，根据算法，分别设置对应的波特率。相关算法请看另外一篇文章。
if (highspeed < 3) { /*0~2*/
/* Set divisor DLL and DLH */
divisor = uartclk / (quot * speed);
remainder = uartclk % (quot * speed);
if (remainder >= (quot / 2) * speed)
divisor += 1;
mt65xx_reg_sync_writew(highspeed, UART_HIGHSPEED(g_uart));
byte = DRV_Reg32(UART_LCR(g_uart)); /* DLAB start 读取UART_LCR 寄存器的值*/
mt65xx_reg_sync_writel((byte | UART_LCR_DLAB), UART_LCR(g_uart));
mt65xx_reg_sync_writel((divisor & 0x00ff), UART_DLL(g_uart));
mt65xx_reg_sync_writel(((divisor >> 8)&0x00ff), UART_DLH(g_uart));
mt65xx_reg_sync_writel(byte, UART_LCR(g_uart)); /* DLAB end */
}
else {
data=(unsigned short)(uartclk/speed);
high_speed_div = (data>>8) + 1; // divided by 256
tmp_div=uartclk/(speed*high_speed_div);
divisor = (unsigned short)tmp_div;
remainder = (uartclk)%(high_speed_div*speed);
/*get (sample_count+1)*/
if (remainder >= ((speed)*(high_speed_div))>>1)
divisor = (unsigned short)(tmp_div+1);
else
divisor = (unsigned short)tmp_div;
sample_count=divisor-1;
/*get the sample point*/
sample_point=(sample_count-1)>>1;
/*configure register*/
mt65xx_reg_sync_writel(highspeed, UART_HIGHSPEED(g_uart));
byte = DRV_Reg32(UART_LCR(g_uart)); /* DLAB start */
mt65xx_reg_sync_writel((byte | UART_LCR_DLAB), UART_LCR(g_uart));
mt65xx_reg_sync_writel((high_speed_div & 0x00ff), UART_DLL(g_uart));
mt65xx_reg_sync_writel(((high_speed_div >> 8)&0x00ff), UART_DLH(g_uart));
mt65xx_reg_sync_writel(sample_count, UART_SAMPLE_COUNT(g_uart));
mt65xx_reg_sync_writel(sample_point, UART_SAMPLE_POINT(g_uart));
mt65xx_reg_sync_writel(byte, UART_LCR(g_uart)); /* DLAB end */
}
}
//设置当前使用的串口（串口1/串口2）
/*
mediatek/platform/mt6572/lk/include/platform/mt_uart.h:
typedef enum
{
UART1 = UART1_BASE,
UART2 = UART2_BASE
} MTK_UART;
mediatek/platform/mt6572/lk/include/platform/mt_reg_base.h:#define UART1_BASE 0x11005000 //MT6572
*/
void mtk_set_current_uart(MTK_UART uart_base)
{
switch(uart_base)
{
case UART1 :
g_uart = uart_base;
break;
case UART2 :
g_uart = uart_base;
break;
default:
ASSERT(0);
break;
}
}
extern BOOT_ARGUMENT *g_boot_arg;
void
uart_init_early(void)
{
#ifdef __ENABLE_UART_LOG_SWITCH_FEATURE__ //走if分支
if(get_uart_port_id() == 1){// 如果是使用串口1，则设置串口基地址为UART1的寄存器基地址 // MT6572的工程配置了log从UART1输出。
#ifdef GPIO_UART_URXD1_PIN //GPIO103
mt_set_gpio_mode(GPIO_UART_URXD1_PIN, GPIO_MODE_01);
mt_set_gpio_mode(GPIO_UART_UTXD1_PIN, GPIO_MODE_01); //GPIO104 ->GPIO_UART_UTXD1_PIN
#endif
mtk_set_current_uart(UART1); // 设置当前串口为 UART1
mtk_uart_power_on(UART1);// 打开UART1的相关的电源
}else{
#ifdef GPIO_UART_URXD2_PIN
mt_set_gpio_mode(GPIO_UART_URXD2_PIN, GPIO_MODE_01);
mt_set_gpio_mode(GPIO_UART_UTXD2_PIN, GPIO_MODE_01);
#endif
mtk_set_current_uart(UART2);
mtk_uart_power_on(UART2);
}
#else
mtk_set_current_uart(UART2);
mtk_uart_power_on(UART2);
#endif
/*[MT6572] workaround set all uart port to AP in META_mode*/
if((g_boot_arg->boot_mode &= 0x000000FF) == META_BOOT){
// 如果是 META_BOOT 模式启动，则做如下操作.Meta模式使用UART1。
if((g_boot_arg->meta_com_type &= 0x000000FF) == META_UART_COM){
#ifdef GPIO_UART_URXD1_PIN // 如果 meta_com_type 为 META_UART_COM，那么设置UART1的两个PIN脚为GPIO模式。
mt_set_gpio_mode(GPIO_UART_URXD1_PIN, GPIO_MODE_01);
mt_set_gpio_mode(GPIO_UART_UTXD1_PIN, GPIO_MODE_01);
#endif
mtk_set_current_uart(UART1);// 设置当前使用串口的基地址, 基地址保存在g_uart 变量。
mtk_uart_power_on(UART1);
}
}
/*[MT6572] workaround end*/
/*
// #define UART_FCR(uart) (UART_BASE(uart)+0x8) // 串口的FCR寄存器，地址位于串口寄存器的基地址偏移0x8也就是第3个寄存器。
//mediatek/platform/mt6572/lk/include/platform/mt_uart.h:
#define UART_FCR_FIFO_INIT (UART_FCR_FIFOE|UART_FCR_CLRR|UART_FCR_CLRT)
*/
使能串口FIFO（FCR: FIFO CONTROL REGISTER）,clear TX FIFO, clear RX FIFO.
DRV_SetReg32(UART_FCR(g_uart), UART_FCR_FIFO_INIT); /* clear fifo */
/* LCR: Line Control Register.
UART_NONE_PARITY:(0 << 3); // 奇偶校验: (0:不检查，1:检查)
UART_1_STOP:(0 << 2); // 发送的时候添加的停止位的位数。(0:1, 1:2bit)
UART_WLS_8:(3 << 0), 选择word的长度为8bit (0:5, 1:6, 2:7, 3:8bit)
*/
mt65xx_reg_sync_writew(UART_NONE_PARITY | UART_WLS_8 | UART_1_STOP, UART_LCR(g_uart));
g_brg = CONFIG_BAUDRATE; // 921600
//串口1的初始化配置：设置串口波特率...
uart_setbrg();
}
void uart_init(void)
{
}
//通过串口发送单个字符
int uart_putc(const char c )
{
/*
#define UART_LSR(uart) (UART_BASE(uart)+0x14)
mediatek/platform/mt6572/lk/include/platform/mt_uart.h:#define UART_LSR_THRE (1 << 5)
mediatek/platform/mt6572/lk/include/platform/mt_typedefs.h:
#define READ_REGISTER_UINT32(reg) (*(volatile unsigned int * const)(reg))
#define INREG32(x) READ_REGISTER_UINT32((unsigned int *)(x))
#define DRV_Reg32(addr) INREG32(addr)// 含义：就是吧 addr地址 的数据读取出来。
*/
while (!(DRV_Reg32(UART_LSR(g_uart)) & UART_LSR_THRE));
if (c == '\n')
mt65xx_reg_sync_writel((unsigned int)'\r', UART_THR(g_uart));
mt65xx_reg_sync_writel((unsigned int)c, UART_THR(g_uart)); // THR 串口发送寄存器。
return 0;
}
//通过串口接受字符
int uart_getc(void) /* returns -1 if no data available */
{
while (!(DRV_Reg32(UART_LSR(g_uart)) & UART_LSR_DR));
return (int)DRV_Reg32(UART_RBR(g_uart));// RBR 串口接收寄存器。
}
//通过串口传输字符串;
void uart_puts(const char *s)
{
while (*s)
uart_putc(*s++);
}
#ifdef __ENABLE_UART_LOG_SWITCH_FEATURE__
extern BOOT_ARGUMENT *g_boot_arg;
int get_uart_port_id(void)
{
unsigned int mode = 0;
unsigned int log_port;
unsigned int log_enable;
unsigned int log_baudrate;
mode = g_boot_arg->boot_mode &= 0x000000FF;
log_port = g_boot_arg->log_port;
log_enable = g_boot_arg->log_enable;
log_baudrate = g_boot_arg->log_baudrate;
if( (log_port == UART1)&&(log_enable != 0) )
return 1;
return 2;
}
static void change_uart_port(char * cmd_line, char new_val)
{
int i;
int len;
char *ptr;
if(NULL == cmd_line)
return;
len = strlen(cmd_line);
ptr = cmd_line;
i = strlen("ttyMT");
if(len < i)
return;
len = len-i;
for(i=0; i<=len; i++)
{
if(strncmp(ptr, "ttyMT", 5)==0)
{
ptr[5] = new_val; // Find and modify
break;
}
ptr++;
}
}
void custom_port_in_kernel(BOOTMODE boot_mode, char *command)
{
if(get_uart_port_id() == 1){
change_uart_port(command, '0');
}
}
#else
void custom_port_in_kernel(BOOTMODE boot_mode, char *command)
{
// Dummy function case
}
int get_uart_port_id(void)
{
// Dummy function case
}
#endif
/*
FILENAME: mediatek/platform/mt6572/lk/include/platform/mt_uart.h
Copyright Statement:
*
* This software/firmware and related documentation ("MediaTek Software") are
* protected under relevant copyright laws. The information contained herein
* is confidential and proprietary to MediaTek Inc. and/or its licensors.
* Without the prior written permission of MediaTek inc. and/or its licensors,
* any reproduction, modification, use or disclosure of MediaTek Software,
* and information contained herein, in whole or in part, shall be strictly prohibited.
*
* MediaTek Inc. (C) 2010. All rights reserved.
*
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*
* The following software/firmware and/or related documentation ("MediaTek Software")
* have been modified by MediaTek Inc. All revisions are subject to any receiver's
* applicable license agreements with MediaTek Inc.
*/
#ifndef ___MTK_UART_H__
#define ___MTK_UART_H__
#include <platform/mt_reg_base.h>
typedef enum
{
UART1 = UART1_BASE,
UART2 = UART2_BASE
} MTK_UART;
#define UART_FIFO_SIZE (16)
#define IO_OFFSET (0)
/* IER */
#define UART_IER_ERBFI (1 << 0) /* RX buffer conatins data int. */
#define UART_IER_ETBEI (1 << 1) /* TX FIFO threshold trigger int. */
#define UART_IER_ELSI (1 << 2) /* BE, FE, PE, or OE int. */
#define UART_IER_EDSSI (1 << 3) /* CTS change (DCTS) int. */
#define UART_IER_XOFFI (1 << 5)
#define UART_IER_RTSI (1 << 6)
#define UART_IER_CTSI (1 << 7)
#define UART_IER_ALL_INTS (UART_IER_ERBFI|UART_IER_ETBEI|UART_IER_ELSI|\
UART_IER_EDSSI|UART_IER_XOFFI|UART_IER_RTSI|\
UART_IER_CTSI)
#define UART_IER_HW_NORMALINTS (UART_IER_ERBFI|UART_IER_ELSI|UART_IER_EDSSI)
#define UART_IER_HW_ALLINTS (UART_IER_ERBFI|UART_IER_ETBEI| \
UART_IER_ELSI|UART_IER_EDSSI)
/* FCR */
#define UART_FCR_FIFOE (1 << 0)
#define UART_FCR_CLRR (1 << 1)
#define UART_FCR_CLRT (1 << 2)
#define UART_FCR_DMA1 (1 << 3)
#define UART_FCR_RXFIFO_1B_TRI (0 << 6)
#define UART_FCR_RXFIFO_6B_TRI (1 << 6)
#define UART_FCR_RXFIFO_12B_TRI (2 << 6)
#define UART_FCR_RXFIFO_RX_TRI (3 << 6)
#define UART_FCR_TXFIFO_1B_TRI (0 << 4)
#define UART_FCR_TXFIFO_4B_TRI (1 << 4)
#define UART_FCR_TXFIFO_8B_TRI (2 << 4)
#define UART_FCR_TXFIFO_14B_TRI (3 << 4)
#define UART_FCR_FIFO_INIT (UART_FCR_FIFOE|UART_FCR_CLRR|UART_FCR_CLRT)
#define UART_FCR_NORMAL (UART_FCR_FIFO_INIT | \
UART_FCR_TXFIFO_4B_TRI| \
UART_FCR_RXFIFO_12B_TRI)
/* LCR */
#define UART_LCR_BREAK (1 << 6)
#define UART_LCR_DLAB (1 << 7)
#define UART_WLS_5 (0 << 0)
#define UART_WLS_6 (1 << 0)
#define UART_WLS_7 (2 << 0)
#define UART_WLS_8 (3 << 0)
#define UART_WLS_MASK (3 << 0)
#define UART_1_STOP (0 << 2)
#define UART_2_STOP (1 << 2)
#define UART_1_5_STOP (1 << 2) /* Only when WLS=5 */
#define UART_STOP_MASK (1 << 2)
#define UART_NONE_PARITY (0 << 3)
#define UART_ODD_PARITY (0x1 << 3)
#define UART_EVEN_PARITY (0x3 << 3)
#define UART_MARK_PARITY (0x5 << 3)
#define UART_SPACE_PARITY (0x7 << 3)
#define UART_PARITY_MASK (0x7 << 3)
/* MCR */
#define UART_MCR_DTR (1 << 0)
#define UART_MCR_RTS (1 << 1)
#define UART_MCR_OUT1 (1 << 2)
#define UART_MCR_OUT2 (1 << 3)
#define UART_MCR_LOOP (1 << 4)
#define UART_MCR_XOFF (1 << 7) /* read only */
#define UART_MCR_NORMAL (UART_MCR_DTR|UART_MCR_RTS)
/* LSR */
#define UART_LSR_DR (1 << 0)
#define UART_LSR_OE (1 << 1)
#define UART_LSR_PE (1 << 2)
#define UART_LSR_FE (1 << 3)
#define UART_LSR_BI (1 << 4)
#define UART_LSR_THRE (1 << 5)
#define UART_LSR_TEMT (1 << 6)
#define UART_LSR_FIFOERR (1 << 7)
/* MSR */
#define UART_MSR_DCTS (1 << 0)
#define UART_MSR_DDSR (1 << 1)
#define UART_MSR_TERI (1 << 2)
#define UART_MSR_DDCD (1 << 3)
#define UART_MSR_CTS (1 << 4)
#define UART_MSR_DSR (1 << 5)
#define UART_MSR_RI (1 << 6)
#define UART_MSR_DCD (1 << 7)
/* EFR */
#define UART_EFR_EN (1 << 4)
#define UART_EFR_AUTO_RTS (1 << 6)
#define UART_EFR_AUTO_CTS (1 << 7)
#define UART_EFR_SW_CTRL_MASK (0xf << 0)
#define UART_EFR_NO_SW_CTRL (0)
#define UART_EFR_NO_FLOW_CTRL (0)
#define UART_EFR_AUTO_RTSCTS (UART_EFR_AUTO_RTS|UART_EFR_AUTO_CTS)
#define UART_EFR_XON1_XOFF1 (0xa) /* TX/RX XON1/XOFF1 flow control */
#define UART_EFR_XON2_XOFF2 (0x5) /* TX/RX XON2/XOFF2 flow control */
#define UART_EFR_XON12_XOFF12 (0xf) /* TX/RX XON1,2/XOFF1,2 flow
control */
#define UART_EFR_XON1_XOFF1_MASK (0xa)
#define UART_EFR_XON2_XOFF2_MASK (0x5)
/* IIR (Read Only) */
#define UART_IIR_NO_INT_PENDING (0x01)
#define UART_IIR_RLS (0x06) /* Receiver Line Status */
#define UART_IIR_RDA (0x04) /* Receive Data Available */
#define UART_IIR_CTI (0x0C) /* Character Timeout Indicator */
#define UART_IIR_THRE (0x02) /* Transmit Holding Register Empty
*/
#define UART_IIR_MS (0x00) /* Check Modem Status Register */
#define UART_IIR_SW_FLOW_CTRL (0x10) /* Receive XOFF characters */
#define UART_IIR_HW_FLOW_CTRL (0x20) /* CTS or RTS Rising Edge */
#define UART_IIR_FIFO_EN (0xc0)
#define UART_IIR_INT_MASK (0x1f)
/* RateFix */
#define UART_RATE_FIX (1 << 0)
//#define UART_AUTORATE_FIX (1 << 1)
//#define UART_FREQ_SEL (1 << 2)
#define UART_FREQ_SEL (1 << 1)
#define UART_RATE_FIX_13M (1 << 0) /* means UARTclk = APBclk / 4 */
#define UART_AUTORATE_FIX_13M (1 << 1)
#define UART_FREQ_SEL_13M (1 << 2)
#define UART_RATE_FIX_ALL_13M (UART_RATE_FIX_13M|UART_AUTORATE_FIX_13M| \
UART_FREQ_SEL_13M)
#define UART_RATE_FIX_26M (0 << 0) /* means UARTclk = APBclk / 2 */
#define UART_AUTORATE_FIX_26M (0 << 1)
#define UART_FREQ_SEL_26M (0 << 2)
#define UART_RATE_FIX_ALL_26M (UART_RATE_FIX_26M|UART_AUTORATE_FIX_26M| \
UART_FREQ_SEL_26M)
#define UART_RATE_FIX_32M5 (0 << 0) /* means UARTclk = APBclk / 2 */
#define UART_FREQ_SEL_32M5 (0 << 1)
#define UART_RATE_FIX_ALL_32M5 (UART_RATE_FIX_32M5|UART_FREQ_SEL_32M5)
#define UART_RATE_FIX_16M25 (0 << 0) /* means UARTclk = APBclk / 4 */
#define UART_FREQ_SEL_16M25 (0 << 1)
#define UART_RATE_FIX_ALL_16M25 (UART_RATE_FIX_16M25|UART_FREQ_SEL_16M25)
/* Autobaud sample */
#define UART_AUTOBADUSAM_13M 7
#define UART_AUTOBADUSAM_26M 15
#define UART_AUTOBADUSAM_52M 31
//#define UART_AUTOBADUSAM_52M 29 /* 28 or 29 ? */
#define UART_AUTOBAUDSAM_58_5M 31 /* 31 or 32 ? */
extern void mtk_set_current_uart(MTK_UART uart_base);
#endif /* !__MT65XX_UART_H__ */