The 3 Port Switch Ethernet Subsystem generates four interrupt events.
这个三个端口的可变式以太网子系统可产生四个中断事件
14.3.1.3.1 Receive Packet Completion Pulse Interrupt (RX_PULSE)
接受数据包脉冲完成中断（RX_PULSE）
The RX_PULSE interrupt is a paced pulse interrupt selected from the 3PSW RX_PEND [7:0] interrupts.
接受数据包脉冲中断是一个节奏的脉冲中断来自于 3PSW RX_PEND [7:0] 的中断
The receive DMA controller has eight channels with each channel having a corresponding
(RX_PEND[7:0]).
一个产生的DMA控制器有八个通道并且每个通道都有对应的（RX_PEND）
The following steps will enable the receive packet completion interrupt.
下面的步骤将使能接受数据完成中断
• Enable the required channel interrupts of the DMA engine by setting 1 to the appropriate bit in the
RX_INTMASK_SET register.
使能这个需要DMA控制器的频道中断，是通过设置1到适当的位在RX_INTMASK_SET寄存器
• The receive completion interrupt(s) to be routed to RX_PULSE is selected by setting one or more bits
in the receive interrupt enable register Cn_RX_EN. The masked interrupt status can be read in the
Receive Interrupt Masked Interrupt Status (Cn_RX_STAT) register.
接受完成中断将被跟踪到RX_PULSE，被选择通过设置一位或者多位在接受中断使能寄存器Cn_RX_EN。这个屏蔽中断的状态可以被读取在接受屏蔽中断的状态（Cn_Rx_STAT）
When the 3PSW completes a packet reception, the subsystem issues an interrupt to the CPU by writing
the packet's last buffer descriptor address to the appropriate channel queue's receive completion pointer
located in the state RAM block. The interrupt is generated by the write when enabled by the interrupt
mask, regardless of the value written.
当3psw完成一个数据包的接受时，这个子系统发出一个中断给CPU通过写入数据包的最后一个缓冲区的指示指向到一个恰当的频道队列指向当地的状态RAM块。这个中断将产生通过写入，当使能中断屏蔽，也不管是不是有有效数据
Upon interrupt reception, the CPU processes one or more packets from the buffer chain and then
acknowledges one or more interrupt(s) by writing the address of the last buffer descriptor processed to the
queue's associated receive completion pointer (RXn_CP) in the receive DMA state RAM.
依据中断接受，cpu处理一个或者多个数据包从缓冲区链然后承认一个或者多个中断通过写入最后一个缓冲区的描述的地址，处理给队列与完成DMA状态的RAM相关的。
Upon reception of an interrupt, software should perform the following:
根据接受的中断，软件还应该有下面的表现：
• Read the RX_STAT register to determine which channel(s) caused the interrupt.
读取RX_STAT寄存器来确定那个贫道产生了中断。
• Process received packets for the interrupting channel(s).
处理产生中断了的频道接受的数据包。
• Write the 3PSW completion pointer(s) (RXn_CP). The data written by the host (buffer descriptor
address of the last processed buffer) is compared to the data in the register written by the subsystem
(address of last buffer descriptor used by the subsystem). If the two values are not equal (which means
that the 3PSW has received more packets than the CPU has processed), the receive packet
completion interrupt signal remains asserted. If the two values are equal (which means that the host
has processed all packets that the system has received), the pending interrupt is de-asserted. The
value that the 3PSW is expecting is found by reading the receive channeln completion pointer register
(RXn_CP).
写入3PSE完成的指针，这个数据是由主站写入的（缓冲区的描述对应着最后一个缓冲区的描述，被子系统所用），如果两个值是不相等的，3psw已经接收到比CPU能处理的更多的数据包，这个接受的数据包完成标志将会保持有效，如果两个值是相等的，那么就说明主机处理所有的数据包，他是系统所有接受的，这个值3PSW系统被发现的，通过读取接受频道完成指针寄存器（RXn_CP）
• Write the value 1h to the CPDMA_EOI_VECTOR register.
To disable the interrupt:
• The eight channel interrupts may be individually disabled by writing to 1 the appropriate bit in the
RX_INTMASK_CLEAR
禁止 这8个频道的中断，通过写入1到对应的RX_INTMASK_CLEAR的位置
• The receive completion pulse interrupt could be disabled by clearing to 0 all the bits of the RX_EN.
The software could still poll for the RX_INTSTAT_RAW and RX_INTSTAT_MASKED registers if the
corresponding interrupts are enabled.
接受完成脉冲中断可以被禁止通过清零到对应的RX_EN位置。这个软件将得到RX_INTSTAT_RAW和RX_INTSTAT_MASKED寄存器如果相应的中断被使能
14.3.1.3.2 Transmit Packet Completion Pulse Interrupt (TX_PULSE)
The TX_PULSE interrupt is a paced pulse interrupt selected from the 3PSW TX_PEND [7:0] interrupts.
TX_PULSE中断是一个节奏性的中断，通过选中3PSW TX_PEND[7:0]中断。
The transmit DMA controller has eight channels with each channel having a corresponding
(TX_PEND[7:0]).
发送的DMA控制器有8个频道，每个频道相对应这（TX_PEND[7:0]）
To enable the transmit packet completion interrupt:
• Enable the required channel interrupts of the DMA engine by setting 1 to the appropriate bit in the
TX_INTMASK_SET register.
使能发送数据包完成中断，使能需要的频道中断，DMA控制器通过设置1到TX_INTMASK_SET寄存器适当的位置。
• The transmit completion interrupt(s) to be routed to TX_PULSE is selected by setting one or more bits
in the transmit interrupt enable register Cn_TX_EN .The masked interrupt status can be read in the
Transmit Interrupt Masked Interrupt Status (Cn_TX_STAT) register