module test
(
input clk,
input rst_n,
input a,
output reg c
);
reg b,rst_nr;
always @ (posedge clk)
rst_nr <= rst_n;
always @ (posedge clk or negedge rst_nr)
if(!rst_nr) b <= 1'b0;
else b <= a;
always @ (posedge clk or negedge rst_nr)
if(!rst_nr) c <= 1'b0;
else c <= b;
endmodule