在ARM v4以后的版本里，ARM核都有7中工作模式：User, FIQ, IRQ, Supervisor, Abort, Undefined,和System。这7中processor mode又分为3类：User mode, Privileged mode和system mode。对于System
mode的作用一直有些模糊，今天在arm的网站上找到了一份说明文档，对这个问题的解析很到位，特记录如下：
5.12. System mode
The ARM Architecture defines a User mode that has 15 general purpose registers, a pc, and a CPSR. In addition to this mode there are five privileged processor modes, each of which have an SPSR and a
number of registers that replace some of the 15 User mode general purpose registers.
Note
This section only applies to processors that implement ARM architectures v4, v4T and later.
When a processor exception occurs, the current program counter is copied into the link register for the exception mode, and the CPSR is copied into the SPSR for the exception mode. The CPSR is then
altered in an exception-dependent way, and the program counter is set to an exception-defined address to start the exception handler.
The ARM subroutine call instruction (BL) copies the return address into r14 before changing the program counter, so the subroutine return instruction moves r14 to pc (MOV pc,lr).
Together these actions imply that ARM modes that handle exceptions must ensure that another exception of the same type cannot occur if they call subroutines, because the subroutine return address will
be overwritten with the exception return address.(In earlier versions of the ARM architecture, this problem has been solved by either carefully avoiding subroutine calls in exception code, or changing from the privileged mode to User mode.The first solution
is often too restrictive, and the second means the task may not have the privileged access it needs to run correctly.)
ARM architecture v4 and later provide a processor mode called system mode, to overcome this problem. System mode is a privileged processor mode that shares the User mode registers. Privileged mode tasks can
run in this mode, and exceptions no longer overwrite the link register.
Note
System mode cannot be entered by an exception. The exception handlers modify the CPSR to enter System mode. See Reentrant interrupt handlers for an example.
就不逐字翻译了，大体意思如下：
当处理器异常出现时，当前程序计数器（也就是 PC+offset，offset与异常种类相关）会被拷贝的相应异常模式的LR，CPSR也会被拷贝到相应异常模式的SPSR。然后CPSR会被设置为 相应的异常模式， PC被设置到对应异常的入口处执行其处理函数。（上面这些都是ARM核自动操作的）
ARM的子程序转移指令BL会在改变PC前将返回地址放到LR中，所以从子程序返回时可以把r14放到PC来操作。如MOV pc, lr。
所有上面的动作都暗示了如果异常处理函数会调用子程序（使用 BL），那么各异常模式都必须保证异常处理函数执行的过程中不能出现同样的异常，因为子函数的返回地址会被异常的返回地址覆盖掉。（在早期的ARM版本 中，可以通过禁止异常处理函数调用子函数或者切换处理模式到User模式来解决这个问题。第一种方式过于严格，而第二种方式可以会由于User模式缺少相 应的权限而不能执行某些动作）。
为此，ARM v4及之后的版本提供了system mode这样一种处理器模式来解决这个问题。System mode是一种privileged的模式，而且共用User模式的所有寄存器。Privileged模式的程序可以运行在这个模式，而不用但是处理器异 常会擦除LR。
注意：
System mode不是因为发生了某种异常处理器自动进入的模式，而是异常处理函数通过修改CPSR来进入的。