学步园

I²
C
（
The Inter-Integrated Circuit
）及其
子集
SMBus
（
System Management Bus
）均为同步串行接口，普遍存在于桌面电脑和嵌入式设备中。
本章通过实现访问
I²
C
EEPROM
和
I²
C
RTC
的驱动实例，让我们理解内核如何支持
I²
C
/SMBus
主机适配器和客户设备。在结束本章之前，让我们也浏览一下内核支持的两种其它的串行接口：串行外围接口（
SPI
）总线和
1-wire
总线。

所有这些串行接口（
I²
C
，
SMBus
，
SPI
和
1-wire
），都有两个共同的特性：

·        


交换的数据总量较少。

·        


数据传输率较低。

i2c_smbus_read_byte()

从设备读取一个字节（不定义位置偏移，使用以前发起的命令的偏移）

i2c_smbus_write_byte()

从设备写入一个字节（使用以前发起的命令的偏移）

i2c_smbus_write_quick()

向设备发送一个比特
(
取代清单
8.1
中的
Rd/Wr
位
).

i2c_smbus_read_byte_data()

从设备指定偏移处读取一个字节

i2c_smbus_write_byte_data()

向设备指定偏移处写入一个字节

i2c_smbus_read_word_data()

从设备指定偏移处读取二个字节

i2c_smbus_write_word_data()

向设备指定偏移处写入二个字节

i2c_smbus_read_block_data()

从设备指定偏移处读取一块数据
.

i2c_smbus_write_block_data()

向设备指定偏移处写入一块数据
. (<= 32
字节
)

Code View:

/* ... */

/*

 
* Connect to the EEPROM. 0x50 is the device address.

 
* smbus_fp is a file pointer into the SMBus device.

 
*/

ioctl(smbus_fp, 0x50, slave);

/* Write a byte (0xAB) at memory offset 0 on the EEPROM */

i2c_smbus_write_byte_data(smbus_fp, 0, 0xAB);

/*

 
* This is the corresponding transaction observed

 
* on the bus after the write:

 
* S 0x50 Wr [A] 0 [A] 0xAB [A] P

 
*

 
* S is the start bit, 0x50 is the 7-bit slave address (0101000b),

 
* Wr is the write command (0b), A is the Accept bit (or

 
* acknowledgment) received by the host from the slave, 0 is the

 
* address offset on the slave device where the byte is to be

 
* written, 0xAB is the data to be written, and P is the stop bit.

 
* The data enclosed within [] is sent from the slave to the

 
* host, while the rest of the bits are sent by the host to the

 
* slave.

 
*/

/* Read a byte from offset 0 on the EEPROM */

res = i2c_smbus_read_byte_data(smbus_fp, 0);

/*

 
* This is the corresponding transaction observed

 
* on the bus after the read:

 
* S 0x50

Wr [A] 0 [A] S 0x50 Rd [A] [0xAB] NA P

 
*

 
* The explanation of the bits is the same as before, except that

 
* Rd stands for the Read command (1b), 0xAB is the data received

 
* from the slave, and NA is the Reverse Accept bit (or the

 
* acknowledgment sent by the host to the slave).

 
*/

Code View:

/* Driver entry points */

static struct file_operations eep_fops = {

 
.owner  
= THIS_MODULE,

 
.llseek 
= eep_llseek,

 
 
.read   
= eep_read,

 
.ioctl  
= eep_ioctl,

 
.open   
= eep_open,

 
.release = eep_release,

 
.write  
= eep_write,

};

static dev_t dev_number;         
/* Allotted Device Number */

static struct class *eep_class;  
/* Device class */

/* Per-device client data structure for each

 
* memory bank supported by the driver

 
*/

struct eep_bank {

 
struct i2c_client *client;     
/* I2C client for this bank */

 
unsigned int addr;             
/* Slave address of this bank */

 
unsigned short current_pointer; /* File pointer */

 
int bank_number;               
/* Actual memory bank number
*/

 
/* ... */                      
/* Spinlocks, data cache for

                                    
slow devices,.. */

};

#define NUM_BANKS 2              
/* Two supported banks */

#define BANK_SIZE 2048           
/* Size of each bank */

struct ee_bank *ee_bank_list;    
/* List of private data

                                    
structures, one per bank */

/*

 
* Device Initialization

 
*/

int __init

eep_init(void)

{

 
int err, i;

 
/* Allocate the per-device data structure, ee_bank */

 
ee_bank_list = kmalloc(sizeof(struct ee_bank)*NUM_BANKS,

                        
GFP_KERNEL);

 
memset(ee_bank_list, 0, sizeof(struct ee_bank)*NUM_BANKS);

 
/* Register and create the /dev interfaces to access the EEPROM

    
banks. Refer back to Chapter 5, "Character Drivers" for

    
more details */

 
if (alloc_chrdev_region(&dev_number, 0,

                         
NUM_BANKS, "eep") < 0) {

   
printk(KERN_DEBUG "Can't register device/n");

   
return -1;

 
}

 
eep_class = class_create(THIS_MODULE, DEVICE_NAME);

 
for (i=0; i < NUM_BANKS;i++) {

   
/* Connect the file operations with cdev */

   
cdev_init(&ee_bank[i].cdev, &ee_fops);

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