library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity docoder_3_to_8 is
port
(
a,b,c,g1,g2a,g2b: in std_logic;
y: out std_logic_vector(7 downto 0)
);
end entity;
architecture rtl of docoder_3_to_8 is
signal indata:std_logic_vector(2 downto 0);
begin
indata<=c&b&a;
process(indata,g1,g2a,g2b)is
begin
if(g1='1'and g2a='0'and g2b='0')then
case indata is
when "000"=>y<="11111110";
when "001"=>y<="11111101";
when "010"=>y<="11111011";
when "011"=>y<="11110111";
when "100"=>y<="11101111";
when "101"=>y<="11011101";
when "110"=>y<="10111101";
when "111"=>y<="01111101";
when others=>y<="XXXXXXXX";
end case;
else
y<="11111111";
end if;
end process;
end architecture rtl;