As follow, I had the problem the same with them:
Question:
I am running a simulation after synthesis and I am getting the following error.
** Error: C:/Modeltech_xe_starter/library/lib18.v(9835): $hold( posedge CK &&& (flag == 1):54 ns, posedge E:54 ns, 500 ps );
lib18.v is a library with various net delays. I dont have anything setup for setup and hold in my verilog testbench. I am getting the same error, no matter what frequency I run the master clock at. How do I get rid of this error? Currenty the master clock is running at 200MHz(4 ns period)
Your help would be appreciated
Answer:
The reported error appears to be a hold time violation which means that the signal is not remaining stable for the required amount of time after the rising edge of the clock. To fix.
1. Identify exactly which signal it is
2. Determine if this is a design error or a modelling error and then apply the appropriate fix.
3. Re-run the simulation.
As a first guess, it is likely that your testbench signals get generated on the rising edge of your clock input and then go into your design. But if the design has some non-zero hold time requirement then the testbench inputs will be changing before the required time and generate the error that you're seeing. This type of problem is frequently a modelling error, your model of the environment in which your design is operating is flawed in that it does represent the real world (no real part would generate an input 0ns after the rising edge of a clock). One way to fix this type of error would be to generate the inputs on the falling edge of the clock.
It's also possible that the input signal truly is asynchronous to your system clock. In this situation, hold time (and setup time) violations are inevitable, your design has to handle the async inputs properly with internal synchronizers but there is no way to get rid of the simulation detecting the violation since it really is occurring. One possible work around though would be to artificially add synchronization to the testbench.
by Kevin Jennings
Solving Setup violation
1. At first check whether the path is a valid path means whether this path will be exercised in your chip or it is a false path.
2. Check with the design specification whether the specified path could operate as a multicycle path rather than a single cycle path.
Assume it is a valid path.
1. Now check the wireload models used .
2. Check the loading of the high fanout nets.
3. group_path -from startpoint -to end point -weightage 100 and ask the tool to concentrate more on the specific paths.
4. use various compile options try with various switches.
5. Use designware components if you have logic similar to adders/multipliers .
6. Use compile_ultra options to speed up the paths which uses different algorithms for optimizations.
7. Use the flip-flops which has lesser setup time.
8. In case if the paths or of cross clock domains check whether the path is of synchronization logic, which usually is a false path as we have synchronizers in these paths.
9. In case you could use low Vt libraries which has faster delays can be used for specific paths to close on timing.check these options whether dual Vt flow is allowed .
10. check whether these paths could be solved in timing by using useful-skew concept after place and route by optimal clocktree building.
Solving hold violation
1. By adding more delay in the data path, by adding buffers.
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